make generally uses variables for this; in particular:
CC specifies the C compiler to use;
CFLAGS specifies C compiler flags to pass the compiler;
LDLIBS specifies libraries to add (although in general you should really write a Makefile which defines everything your program needs to build, which typically includes libraries).
So you'd run
make CFLAGS="-ggdb3 -O0 -std=c99 -Wall -Werror" LDLIBS="-lm" x
to get
cc -ggdb3 -O0 -std=c99 -Wall -Werror x.c -lm -o x
and
make CC="clang" CFLAGS="-ggdb3 -O0 -std=c99 -Wall -Werror" LDLIBS="-lm" x
to get
clang -ggdb3 -O0 -std=c99 -Wall -Werror x.c -lm -o x
You can also set the variables in your environment (which allows defaults to be set in your shell startup scripts):
export CFLAGS="-ggdb3 -O0 -std=c99 -Wall -Werror"
make LDLIBS="-lm" x
Given the absence of a Makefile in your case, you'll probably find How does this Makefile makes C program without even specifying a compiler? interesting! The GNU Make manual will also come in handy.