How Can I Change the Default arguments to gcc When I run Make "filename"

Question

Forgive me if I posted this in the wrong Stack. Every time I run make for a file without any Makefiles in the directory, make still works and compiles the source code but only with the arguments: gcc filename.c -o filename

For example, if I enter make test with test.c in the directory, it does : gcc test.c -o test

I wish to change this, so that ever time I run make without a Makefile, it will instead do : gcc -ggdb -std=c99 -Wall -Werror -o filename filename.c -lcs50 -lm

I also which that this change becomes permanent and does not change regardless if I restart or change directories.

I'm currently running Crunchbang Weezy on an AMD 64bit processor.

Answer 1

You want the CFLAGS environment variable.

For example:

$ export CFLAGS='-ggdb3'
$ make test
cc -ggdb3    test.c   -o test

Answer 2

Generally when you type make test if you're missing a Makefile the make tool will attempt to use a vanilla compile command.

Example

Say we have the following test.c:

$ cat test.c 
#include <stdio.h>
int main()
{
    printf( "I am alive!  Beware.\n" );
    return 0;
}

Without a Makefile when we run make test we'd get the following behavior:

$ make test
cc     test.c   -o test

NOTE: Subsequent runs would result in:

$ make test
make: `test' is up to date.

A test run:

$ ./test 
I am alive!  Beware.

If you're typing make test you must have a Makefile somewhere. When I run that command in a directory that doesn't have a Makefile I get the following:

$ make test
make: *** No rule to make target `test'.  Stop.

Using CFLAGS

If you want to override make's default command line options you can do something like this:

$ export CFLAGS="-ggdb -std=c99 -Wall -Werror -lcs50 -lm"

Now when we run make:

$ make test
cc -ggdb -std=c99 -Wall -Werror -lcs50 -lm    test.c   -o test

References

• Gentoo Wiki CFLAGS
• Introduction to C

Answer 3

[Edit]

From the GNU make man page:

If no -f option is present, make will look for the makefiles GNUmakefile, makefile, and Makefile, in that order.

Passing arguments are only possible if you have a variable for example CFLAGS defined in your Makefile:

CC=gcc
CFLAGS=-g -O -Wall -Werror

all: foo

foo: foo.o
    $(CC) $(CFLAGS) $<

Here you are able to override the variable with

$ make CFLAGS="-ggdb -std=c99 -Wall -Werror"
gcc -ggdb -std=c99 -Wall -Werror   -c -o foo.o foo.c
gcc -ggdb -std=c99 -Wall -Werror foo.o

However, it is easier to edit the Makefile.

Answer 4

That depends on the exact make(1) you have got, and the makefile being used.

For example, GNU make helpfully assumes a set of default rules and macros. I.e., the macro CC gives the name of the C compiler, CXX the C++ one; CFLAGS are flags for CC and CXXFLAGS for CXX.

It also defines a slew of default rules, i.e., to create a foo.o from foo.c by calling $(CC) $(CFLAGS) -c foo.c, and create an executable foo from foo.o by doing $(CC) $(CFLAGS) -o foo foo.o. Again, other versions of make might define other default macros and rules (but CC and CFLAGS seem to be universal).

If there is no makefile, GNU make uses the above rules, and you can override the macros by e.g. creating tst from tst.c with:

make CC=clang CFLAGS='-O2 -g -Wall' tst

Off the top of my head I don't know how other makes react, I seem to remember others just error out when there is no makefile.

If there is a makefile (could be called a few different names, check the manual; at least makefile and Makefile) the macro definitions and rules it defines take over. Most makefiles don't, so you'd get away with the above command. But there are no guarantees. Check for any instructions in files called typically INSTALL, README or some variation, or in the makefile itself.

And finally, there are a few alternatives to make (their default control files are mostly called some variation on makefile), but as make(1) is almost universal, their use should be documented somewhere.